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| il510/il511/il514/il515/il516 isoloop is a registered trademark of nve corporation. *u.s. patent numbers 5, 831,426; 6,300,617 and others. rev. g nve corporation 11409 valley view road, eden prairie, mn 55344-3617 phone: (952) 829-9217 fax: (952) 829-9189 www.isoloop.com ?nve corporation low-cost digital isolators functional diagrams il515 il516 in 1 in 2 out 3 out 4 out 1 out 2 in 3 in 4 out 1 out 2 out 3 out 4 in 1 in 2 in 3 in 4 out 1 in 1 il510 il511 in 1 in 2 out 1 out 2 v oe il514 out 1 out 2 in 1 in 2 in 3 out 3 v oe v oe features ?? +5 v / +3.3 v cmos/ttl compatible ?? 2 mbps maximum speed ?? ? 40oc to 85oc operating temperature ?? 2500 v rms isolation (1 min.) ?? 10 ns pulse width distortion ?? 25 ns propagation delay ?? dc-correct ?? 30 kv/s typical common mode rejection ?? low emc footprint ?? 8-pin msop; 0.3" and 0.15" 8-p in and 16-pin soic packages ?? ul 1577 and iec 61010-2001 approved applications ?? adcs and dacs ?? digital fieldbus ?? rs-485 and rs-422 ?? multiplexed data transmission ?? data interfaces ?? board-to-board communication ?? digital noise reduction ?? ground loop elimination ?? peripheral interfaces ?? parallel bus ?? logic level shifting description il500-series isolators are low cost isolators operating up to 2mbps over an operating temperature range of ? 40oc to 85oc. the devices use nve?s patented* isoloop ? spintronic giant magnetoresistive (gmr) technology.
il510/il511/il514/il515/il516 2 absolute maximum ratings parameters symbol min. typ. max. units test conditions storage temperature t s ? 55 150 c ambient operating temperature (1) t a ? 55 150 c supply voltage v dd 1 , v dd 2 ? 0.5 7 v input voltage v i ? 0.5 v dd +0.5 v output voltage v o ? 0.5 v dd +0.5 v output current drive i o 10 ma lead solder temperature 260 c 10 sec. esd 2 kv hbm recommended operating conditions parameters symbol min. typ. max. units test conditions ambient operating temperature t a ? 40 85 c supply voltage v dd 1 , v dd 2 3.0 5.5 v logic high input voltage v ih 2.4 v dd v logic low input voltage v il 0 0.8 v input signal rise and fall times (10) t ir , t if dc-correct insulation specifications parameters symbol min. typ. max. units test conditions creepage distance msop 3.0 mm 0.15" soic (8-pin or 16-pin) 4.0 mm 0.3" soic 8.1 mm leakage current 0.2 a 240 v rms , 60 hz barrier impedance >10 14 ||3 ? || pf package characteristics parameters symbol min. typ. max. units test conditions capacitance (input?output) (5) c i ? o 4 pf f = 1 mhz thermal resistance msop jc 168 c/w 0.15" 8-pin soic jc 144 c/w 0.15" 16-pin soic jc 41 c/w 0.3" 16-pin soic jc 28 c/w thermocouple at center underside of package package power dissipation p pd 150 mw f = 1 mhz, v dd = 5 v safety and approvals iec61010-1 tuv certificate numbers: n1502812, n1502812-101 classification as reinforced insulation model package pollution degree material group max. working voltage il5xx-1 msop ii iii 150 v rms il5xx-3 8-pin and 16-pin 0.15" soic ii iii 150 v rms il5xx 0.3" soic ii iii 300 v rms ul 1577 component recognition program file number: e207481 rated 2500v rms for 1 minute soldering profile per jedec j-std-020c, msl=2 il510/il511/il514/il515/il516 3 il510 pin connections 1 v dd1 supply voltage 2 in data in 3 sync internal refresh clock disable (normally enabled and internally held low with 10 k ? ) 4 gnd 1 ground return for v dd1 5 gnd 2 ground return for v dd2 6 out data out 7 v oe output enable (internally held low with 100 k ? ) 8 v dd2 supply voltage v dd1 v dd2 in v oe sync out gnd 1 gnd 2 il510 il511 pin connections 1 v dd1 supply voltage 2 in 1 data in, channel 1 3 in 2 data in, channel 2 4 gnd 1 ground return for v dd1 5 gnd 2 ground return for v dd2 6 out 2 data out, channel 2 7 out 1 data out, channel 1 8 v dd2 supply voltage 1 2 3 45 6 7 8 in 1 in 2 v dd1 gnd 1 out 2 out 1 v dd2 gnd 2 il511 il514 pin connections 1 v dd1 supply voltage 1 2 gnd 1 ground return for v dd1 (internally connected to pin 8) 3 in 1 data in, channel 1 4 in 2 data in, channel 2 5 out 3 data out, channel 3 6 nc no connection 7 v oe output enable, channel 3 (internally held low with 100 k ? ) 8 gnd 1 ground return for v dd1 (internally connected to pin 2) 9 gnd 2 ground return for v dd2 (internally connected to pin 15) 10 nc no connection 11 nc no connection 12 in 3 data in, channel 3 13 out 2 data out, channel 2 14 out 1 data out, channel 1 15 gnd 2 ground return for v dd2 (internally connected to pin 9) 16 v dd2 supply voltage v dd1 gnd 1 gnd 2 in 1 out 1 out 2 in 2 v dd2 nc in 3 gnd 1 gnd 2 nc v oe out 3 nc il514 il510/il511/il514/il515/il516 4 il515 pin connections 1 v dd1 supply voltage 2 gnd 1 ground return for v dd 1 3 in 1 data in, channel 1 4 in 2 data in, channel 2 5 in 3 data in, channel 3 6 in 4 data in, channel 4 7 sync internal refresh clock disable (normally enabled and internally held low with 10 k ? ) 8 gnd 1 ground return for v dd 1 9 gnd 2 ground return for v dd 2 10 v oe output enable (internally held low with 100 k ? ) 11 out 4 data out, channel 4 12 out 3 data out, channel 3 13 out 2 data out, channel 2 14 out 1 data out, channel 1 15 gnd 2 ground return for v dd 2 16 v dd2 supply voltage v dd1 gnd 1 gnd 2 out 2 out 3 out 1 in 1 in 2 in 3 v dd2 in 4 sync out 4 gnd 1 gnd 2 v oe il515 il516 pin connections 1 v dd1 supply voltage 2 gnd 1 ground return for v dd 1 3 in 1 data in, channel 1 4 in 2 data in, channel 2 5 out 3 data out, channel 3 6 out 4 data out, channel 4 7 nc no connection 8 gnd 1 ground return for v dd 1 9 gnd 2 ground return for v dd 2 10 nc no connection 11 in 4 data in, channel 4 12 in 3 data in, channel 3 13 out 2 data out, channel 2 14 out 1 data out, channel 1 15 gnd 2 ground return for v dd 2 16 v dd2 supply voltage v dd1 gnd 1 gnd 2 out 2 out 3 out 1 in 1 in 2 in 3 v dd2 in 4 nc nc out 4 gnd 1 gnd 2 il516 il510/il511/il514/il515/il516 5 timing diagrams legend t plh propagation delay, low to high t phl propagation delay, high to low t pw minimum pulse width t plz propagation delay, low to high impedance t pzh propagation delay, high impedance to high t phz propagation delay, high to high impedance t pzl propagation delay, high impedance to low t r rise time t f fall time truth tables output enable v i v oe v o l l l h l h l h z h h z sync sync internal refresh clock 0 enabled 1 disabled note: sync should be left open or connected to gnd to enable the internal refresh clock, or connected to v dd to disable the internal clock. il510/il511/il514/il515/il516 6 3.3 volt electrical specifications electrical specifications are t min to t max unless otherwise stated. parameters symbol min. typ. max. units test conditions dc specifications input quiescent supply current il510, il511, il515 15 30 a ? il514 1.7 2 ma il516 i dd1 3.3 4 ma output quiescent supply current il510 1.7 2 ma il511, il514, il516 3.3 4 ma il515 i dd2 6.6 8 ma logic input current i i ? 10 10 a v dd ? 0.1 v dd i o = ? 20 a, v i = v ih logic high output voltage v oh 0.8 x v dd 0.9 x v dd v i o = ? 4 ma, v i = v ih 0 0.1 i o = 20 a, v i = v il logic low output voltage v ol 0.5 0.8 v i o = 4 ma, v i = v il switching specifications maximum data rate 2 mbps c l = 15 pf 20 ns v o 50% points; sync=0 pulse width (7) pw 25 ns v o 50% points; sync=1 propagation delay input to output (high to low) t phl 25 ns c l = 15 pf propagation delay input to output (low to high) t plh 25 ns c l = 15 pf propagation delay enable to output (high to high impedance) t phz 5 ns c l = 15 pf propagation delay enable to output (low to high impedance) t plz 5 ns c l = 15 pf propagation delay enable to output (high impedance to high) t pzh 5 ns c l = 15 pf propagation delay enable to output (high impedance to low) t pzl 5 ns c l = 15 pf pulse width distortion (2) pwd 10 ns c l = 15 pf propagation delay skew (3) t psk 10 ns c l = 15 pf output rise time (10% ? 90%) t r 1 3 ns c l = 15 pf output fall time (10% ? 90%) t f 1 3 ns c l = 15 pf common mode transient immunity (output logic high or logic low) (4) |cm h |,|cm l | 20 30 kv/s v cm = 300 v channel-to-channel skew t csk 3 5 ns c l = 15 pf sync internal clock off time (11) t off 5 ns dynamic power consumption (6) 140 240 a/mhz per channel magnetic field immunity (8) (v dd2 = 3v, 3v il510/il511/il514/il515/il516 9 application information electrostatic discharge sensitivity this product has been tested for electrostatic sensitivity to the limits stated in the specifications. however, nve recommends that all integrated circuits be handled with appropriate care to avoid damage. damage caused by inapprop riate handling or storage could range from performance degradation to complete failure. electromagnetic compatibility isoloop isolators have the lowest emc footprint of any isolation technology. isoloop isolators? wheatstone bridge configuration and differential magnetic field signaling ensure excellent emc performance against all relevant standards. additionally, on the il510 and il515, the internal clock can be disabled for even better emc performance. these isolators are fully complia nt with generic emc standards en50081, en50082-1 and the umbrella line-voltage standard for information technology equipment (ite) en61000. nve has completed compliance tests in the categories below: en50081-1 residential, commercial & light industrial methods en55022, en55014 en50082-2: industrial environment methods en61000-4-2 (esd), en61000-4-3 (electromagnetic field immunity), en61000-4-4 (electrical transient immunity), en61000-4-6 (rfi immunity), en61000-4-8 (power frequency magnetic field immunity), en61000-4-9 (pulsed magnetic field), en61000-4-10 (damped osc illatory magnetic field) env50204 radiated field from digital telephones (immunity test) immunity to external magnetic fiel ds is even higher if the field direction is ?end-to-end? rather than to ?pin-to-pin? as shown in the diagram below: cross-axis field direction dynamic power consumption isoloop isolators achieve their low power consumption from the way they transmit data across the isolation barrier. a magnetic field is created around the gmr wheatstone bridge by detecting the edge transitions of the input logic signal and converting them to narrow current pulses. depending on the direction of the magnetic field, the bridge causes the output comparator to switch following the input logic signal. since the current pulses are narrow, about 2.5 ns, the power consumption is independent of mark-to-space ratio and solely dependent on frequency. this has obvious advantages over optocouplers, wh ich have power consumption heavily dependent on mark-to-space ratio. power supply decoupling both power supplies to these devices should be decoupled with low esr ceramic capacitors of at least 47 nf. capacitors must be located as close as possible to the v dd pins. dc correctness, emc, and the sync function nve digital isolators have the lowest emc noise signature of any high-speed digital isolator on the market today because of the dc nature of the gmr sensors used. it is perhaps fair to include opto- couplers in that dc category too, but their limited parametric performance, physically large size, and wear-out problems effectively limit side by side co mparisons between nve?s isolators and isolators coupled with rf, ma tched capacitors, or transformers. il500-series isolators has an inte rnal refresh clock which ensure the synchronization of input and output within 9 s of the supply passing the 1.5 v threshold. the il510 and il515 allow external control of the refresh clock through the sync pin thereby further lowering the emc footprint. this can be advantageous in applications such as hi-fi, motor control and power conversion. the isolators can be used with power on reset (por) circuits common in microcontroller applications, as the means of ensuring the output of the device is in the same state as the input a short time after power up. figure 1 shows a practical power on reset circuit: por set out sync in 1 2 3 4 8 6 5 il510 v oe 7 v dd1 v dd2 fig. 1. typical power on reset circuit for il510 after por, the sync line goes high , the internal clock is disabled, and the emc signature is optimized. decoupling capacitors are omitted for clarity. il510/il511/il514/il515/il516 10 illustrative applications isolated a/d converter bridge + iso sd out iso cs iso sck bridge - osc il514 cs5532 clock generator bridge bias delta sigma a/d sd out cs sck sd oe a delta-sigma a-d converter interfaced with the three-channel il514. multiple channels can easily be combined using the il514?s output enable function. il510/il511/il514/il515/il516 11 12-bit d/a converter isolation d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 oe oe oe sync reset data bus latch v out 12-bit dac 3 x il515 latch latch sync sync the il515 four-channel isolator is ideally suited for parallel bus isol ation. the circuit above uses three il515s to isolate a 12-bit dac. the unique sync function automatically synchronizes the outputs to the inputs, ens ureing correct data on the isolator outputs. after the reset pulse goes high, data transfer from input to output is initiated by the leading edge of each changing data bit. intelligent dc-dc converter with synchronous rectification s d g s d s d g g microcontroller il511 mosfet1 mosfet3 mosfet2 10 vdc a typical primary-side controller uses the il511 to drive the sy nchronous rectification signals from primary side to secondary side. il511 pulse- width distortion of 10 ns minimizes mosfet d ead time and maximizes efficiency. the ultra-small msop package minimizes board are a. il510/il511/il514/il515/il516 12 package drawings, dimensions, and specifications 8-pin msop 0.114 (2.90) 0.114 (2.90) 0.016 (0.40) 0.005 (0.13) 0.009 (0.23) 0.027 (0.70) 0.010 (0.25) 0.028 (0.70) 0.002 (0.05) 0.043 (1.10) 0.032 (0.80) 0.006 (0.15) 0.016 (0.40) 0.024 (0.60) 0.189 (4.80) 0.197 (5.00) 0.122 (3.10) 0.122 (3.10) 6? 0? pin spacing is a basic dimension; tolerances do not accumulate note: 8-pin soic package 0.013 (0.33) 0.020 (0.50) 0.189 (4.8) 0.197 (5.0) 0.150 (3.8) 0.157 (4.0) dimensions in inches (mm) 3 2 1 0.228 (5.8) 0.244 (6.2) 0.008 (0.19) 0.010 (0.25) 0.010 (0.25) 0.020 (0.50) x45o 0o 8o 0.016 (0.40) 0.050 (1.27) 0.040 (1.0) 0.060 (1.5) 0.054 (1.37) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) pin spacing is a basic dimension; tolerances do not accumulate note: il510/il511/il514/il515/il516 13 16-pin 0.15" soic package 0.054 (1.4) 0.072 (1.8) 0.040 (1.0) 0.060 (1.5) 0.016 (0.4) 0.050 (1.3) 0.386 (9.8) 0.394 (10.0) pin 1 identified by either an indent or a marked dot nom 0.228 (5.8) 0.244 (6.2) 0.152 (3.86) 0.157 (3.99) dimensions in inches (mm) 0.007 (0.2) 0.013 (0.3) 0.004 (0.1) 0.012 (0.3) 0.040 (1.02) 0.050 (1.27) 0.013 (0.3) 0.020 (0.5) pin spacing is a basic dimension; tolerances do not accumulate note: 16-pin 0.3" soic package nom pin 1 identified by either an indent or a marked dot 0.287 (7.29) 0.300 (7.62) dimensions in inches (mm) 0.08 (2.0) 0.10 (2.5) 0.092 (2.34) 0.105 (2.67) 0.397 (10.1) 0.413 (10.5) 0.013 (0.3) 0.020 (0.5) 0.394 (10.00) 0.419 (10.64) 0.040 (1.0) 0.060 (1.5) 0.004 (0.1) 0.012 (0.3) 0.007 (0.2) 0.013 (0.3) 0.016 (0.4) 0.050 (1.3) pin spacing is a basic dimension; tolerances do not accumulate note: il510/il511/il514/il515/il516 14 ordering information il 5 16 - 3 e tr13 bulk packaging blank = tube tr7 = 7'' tape and reel tr13 = 13'' tape and reel package blank = 80/20 tin/lead plating e = rohs compliant package type -1 = 8-pin msop -3 = 0.15'' 8-pin or 16-pin soic (not available for il515) blank = 0.30'' 16-pin soic channels 10 = 1 drive channel 11 = 2 drive channels 14 = 2 drive channels; 1 receive channel 15 = 4 drive channels 16 = 2 drive channels; 2 receive channels base part number 5 = 2 mbps, dc-correct product family il = isolators rohs compliant il510/il511/il514/il515/il516 15 isb-ds-001-il500-g november 2010 changes: ?? clarified sync function. isb-ds-001-il500-f changes: ?? changed pin spacing specification on msop drawing. isb-ds-001-il500-e changes: ?? added emc details. isb-ds-001-il500-d changes: ?? add output enable to il515. ?? iec 61010-2001 approval (removed ?pending?). ?? added 12-bit dac illustrative application. isb-ds-001-il500-c production release isb-ds-001-il500-b july 2008 initial release isb-ds-001-il500-a june 2008 preliminary release il510/il511/il514/il515/il516 16 about nve an iso 9001 certified company nve corporation is a high technology component s manufacturer having the unique capability to combine spintronic giant magnetore sistive (gmr) materials with integrated circuits to make high performance electronic components . products include magnetic field sensor s, magnetic field gradient sensors (gradiometer), dig ital magnetic field sensors, digital signal isolators and isolated bus transceivers. nve is a leader in gmr research and in 1994 introduced the world?s first products usin g gmr material, a line of gmr magnetic fi eld sensors that can be used for position, magnetic media, wheel speed and current sensing. nve is located in eden prairie, minnesota, a suburb of minn eapolis. please visit our web site at www.nve.com or call (952) 829-9217 for information on products, sales or distribution. nve corporation 11409 valley view road eden prairie, mn 55344-3617 usa telephone: (952) 829-9217 fax: (952) 829-9189 internet: www.nve.com e-mail: isoinfo@nve.com the information provided by nve corporati on is believed to be accurate. however, no responsibility is assumed by nve corporatio n for its use, nor for any infringement of patents, nor rights or licenses grant ed to third parties, which ma y result from its use. no license is granted by implication, or otherwise, under any patent or patent rights of nve corporation. nve co rporation does not authorize, nor warran t, any nve corporation product for use in life support devices or systems or other critical app lications without the express written appro val of the president of nve corporation. specifications shown are subject to change without notice. isb-ds-001-il500-g november 2010 |
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